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MICRF219
300MHz to 450MHz ASK Receiver with RSSI, Auto-Poll, Bit-Check and Squelch
General Description
Features
The MICRF219 is a 300MHz to 450MHz super* -110dBm sensitivity at 1kbps with BER 10E-02 heterodyne, image-reject, RF receiver with Automatic * Supports data rates up to 10kbps at 433.92MHz Gain Control, OOK/ASK demodulator and analog RSSI * 25dB Image-Reject Mixer output. The device integrates Auto-Poll, Valid Bit-Check, * No IF Filter Required Squelch and Desense features. It only requires a crystal * 60dB Analog RSSI Output and a minimum number of external components to implement. It is ideal for low-cost, low-power, RKE, * 3.0V to 3.6V Supply Voltage Range TPMS, and remote actuation applications. * 4.0mA supply current at 315MHz (continuous receive) The MICRF219 achieves -110dBm sensitivity at a data * 6.0mA supply current at 434MHz (continuous receive) rate of 1kbps (Manchester encoded). Four demodulator * 0.5uA supply current in Shutdown Mode filter bandwidths are selectable in binary steps from * Optional Auto-Polling (sleep mode, current < 0.1mA) 1625Hz to 13kHz at 433MHz, allowing the device to support data rates to 10kbps. The device operates from * Optional Valid Bit-Check in Auto-Poll Mode a supply voltage of 3.0V to 3.6V, and consumes 4.0mA * Optional Programmable 6dB to 42dB Desense of supply current at 315MHz and 6.0mA at 433.92MHz. * Optional Data Output Squelch until valid bits detected A shutdown mode reduces supply current to 0.5uA. The * 16-pin QSOP Package (4.9mm x 6.0mm) Auto-Polling feature allows the MICRF219 to sleep and poll for user defined periods, thus further reducing * -40C to +105C Temperature Range supply current. The Valid Bit-Check feature, when * 2kV HBM ESD Rating enabled in Auto-Poll mode, fully awakes the receiver * Evaluation board QR219BPF Available and sends bits to the microcontroller once a valid number of bits are detected. During normal operation an Ordering Information optional Squelch feature disables the data output until valid bits are detected. An optional Desense feature Part Number Temperature Range Package reduces gain by 6dB to 42dB, distancing the receiver MICRF219AYQS -40C to +105C 16-Pin QSOP from distantly placed, undesired transmitters. _______________________________________________________________________________________________
Typical Application
QwikRadio is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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MICRF219
Pin Configuration
RO1 GNDRF ANT GNDRF Vdd SQ SEL0 SHDN 1 2 3 4 5 6 7 8 16 RO2 15 SCLK 14 RSSI 13 CAGC 12 CTH 11 SEL1 10 DO 9 GND
MICRF219AYQS
Pin Description
16-Pin QSOP 1 P in Name RO1 Pin Function Reference Oscillator Input: Reference resonator input connection to pierce oscillator stage. May also be driven by external reference signal of 200mVp-p to 1.5V p-p amplitude maximum. Internal capacitance of 7pF to GND during normal operation. Negative supply connection associated with ANT RF input. Antenna Input: RF signal input from antenna. Internally AC coupled. It is recommended a matching network with an inductor-to-RF ground be used to improve ESD protection. Ground connection for ANT RF input. Positive supply connection for all chip functions. Bypass with 0.1uF capacitor located as close to the VDD pin as possible. Squelch Control Logic-Level Input. An internal pull-up pulls the logic-input HIGH when the device is enabled. Bit D17 sets whether squelch is enabled or disabled when a logic-level signal is applied the SQ pin. See Squelch Enable Truth-Table on page Demodulator Filter Bandwidth Select Logic-Level Input:) Internal pull-up (3uA typical) when not in shutdown or SLEEP mode. Used in conjunction with SEL1 to control D3 bandwidth LSB when serial interface contains default setting. It does not need to be defined in SLEEP mode. Shutdown control Logic-Level Input. A logic-level LOW enables the device. A logic-level HIGH places the device in low-power shutdown mode. An internal pull-up pulls the logic input HIGH. Negative supply connection for all chip functions except for RF input. Data Input and Output. Demodulated data output. May be blanked until bit checking test is acceptable. A current limited CMOS output during normal operation this pin is also used as a CMOS Schmitt input for serial interface data. A 25k pull-down is present when device is in shutdown and sleep modes. Demodulator Filter Bandwidth Select Logic-Level Input: Internal (3uA typical) pull-up when not in shutdown or SLEEP mode. Used in conjunction with SEL0, to control D4 bandwidth MSB, when serial interface contains default setting. It does not need to be defined in SLEEP mode. Demodulation threshold voltage integration capacitor. Capacitor-to-GND sets the settling time for the demodulation data slicing level. Values above 1nF are recommended and should be optimized for data rate and data profile. AGC filter capacitor. A capacitor, normally greater than 0.47F, is connected from this pin-to-GND Received signal strength indication (output): Output is from a switched capacitor integrating op amp with 220 typical output impedance. Serial interface input clock. CMOS Schmitt input. A 25k pull-down is present when device is in shutdown mode. Reference resonator connection. Internal capacitance of 7pF to GND during normal operation.
2 3 4 5 6
GNDRF ANT GNDRF VDD SQ
7
SEL0
8 9 10
SHDN GND DO
11
SEL1
12
CTH
13 14 15 16
CAGC RSSI SCLK RO2
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Absolute Maximum Ratings(1)
Supply Voltage (VDD) ................................................ +5V Input Voltage. ............................................................. +5V Junction Temperature ...........................................+150C Lead Temperature (soldering, 10sec.) ....................300C Storage Temperature (Ts)...................... -65C to +150C Maximum Receiver Input Power ......................... +10dBm EDS Rating(3) ................................................... 2KV HBM
Operating Ratings(2)
Supply voltage (VDD).............................+3.0V to +3.6V Ambient Temperature (TA) ................. -40C to +105C Input Voltage (Vin) ................................................. 3.6V Maximum Input RF Power................................. -20dBm Receive Modulation Duty Cycle(6) .................... 20~80% Frequency Range...........................300MHz to 450MHz
Electrical Characteristics
Specifications apply for VDD = 3.3V, GND = 0V, CAGC = 4.7F, CTH = 0.1F, fRX = 433.92 MHz unless otherwise noted. Bold values indicate -40C - TA - 105C. 1kbps data rate (Manchester encoded), reference oscillator frequency = 13.52127MHz. Parameter Operating Supply Current Shutdown Current Receiver Image Rejection 1st IF Center Frequency Receiver Sensitivity @ 1kbps (Note 4) IF Bandwidth Antenna Input Impedance Receive Modulation Duty Cycle AGC Attack / Decay Ratio AGC pin leakage current AGC Dynamic Range Reference Oscillator Reference Oscillator Frequency Reference Oscillator Input Impedance fRX = 315 MHz, Crystal Load Cap = 10pF fRX = 433.92 MHz, Crystal Load Cap = 10pF RO1
9.81563
13.52127
Condition Continuous Operation, fRX = 315MHz Continuous Operation, fRX = 433.92MHz
Min
Typ 4.0 6.0 0.15 25
Max
Units mA A dB MHz dBm kHz
fRX = 315MHz fRX = 433.92MHz fRX = 315 MHz, 50 BER=10-2 fRX = 433.92MHz, 50 BER=10 fRX = 315MHz fRX = 433.92MHz fRX = 315MHz fRX = 433.92MHz Note 5 tATTACK / tDECAY TA = 25C TA = +105C RFIN @ -40dBm RFIN @ -100dBm 20
-2
0.86 1.2 -110 -110 235 330
32 - j235 19 - j174
80 0.1 30 800 1.15 1.70
%
nA nA V V
MHz k
1.6
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Micrel Parameter Reference Oscillator Bias Voltage Reference Oscillator Input Range Reference Oscillator Source Current Demodulator CTH Source Impedance CTH Leakage Current Demodulator Filter Bandwidth @ 315MHz Demodulator Filter Bandwidth @ 434MHz DO pin output current Output rise and fall times Input High Voltage Input Low Voltage Output Voltage High Output Voltage Low RSSI RSSI DC Output Voltage Range RSSI response slope RSSI Output Current RSSI Output Impedance RSSI Response Time
Note 1. Note 2. Note 3. Note 4. Note 5.
MICRF219 Condition RO2 0.2 V(REFOSC) = 0V 300 Min Typ 1.15 1.5 Max Units V Vp-p A
FREFOSC = 9.81563 MHz FREFOSC = 13.52127MHz TA = 25C TA = +105C Programmable, see application section Programmable, see application section 1170 1625
165 120 2 800 9400 13000
k nA nA Hz Hz
Digital / Control Functions As output source @ 0.8 Vdd sink @ 0.2 Vdd CI = 15pF, pin DO, 10-90% Pins SCLK, DO (As input), SHDN,SEL0, SEL1,SQ Pins SCLK, DO (As input), SHDN, SEL0, SEL1,SQ DO DO -100dBm -40dBm -110dBm to -40dBm 0.4 2.0 25 400 250 50% data duty cycle, input power to Antenna = -20dBm 0.3 0.8Vdd 0.2Vdd 0.8Vdd 0.2Vdd 260 600 2 A sec V V V V
V
mV/dB
A sec
Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside of its operating rating. Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device. Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is defined as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded) at a data rate of 1kbps. When data burst does not contain preamble, duty cycle is defined as total duty cycle, including any "quiet" time between data bursts. When data bursts contain preamble sufficient to charge the slice level on capacitor CTH, then duty cycle is the effective duty cycle of the burst alone. [For example, 100msec burst with 50% duty cycle, and 100msec "quiet" time between bursts. If burst includes preamble, duty cycle is TON/(TON+tOFF)= 50%; without preamble, duty cycle is TON/(TON+ TOFF + TQUIET) = 50msec/(200msec)=25%. TON is the (Average number of 1's/burst) x bit time, and TOFF = (TBURST - TON.)
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Typical Characteristics
-50 -60 SELECTIVITY (dBm) -70 -80 -90 -100 -110 -120
433MHz Selectivity and Bandwidth by Different Temps.
-40C +105C +20C
433.92MHz V/I by Temperatures
7 105C 6.5 CURRENT (mA) 6 5.5 5 4.5 4 3.0 3.1 3.2 3.3 3.4 VOLTAGE (V) 3.5 3.6 20C -40C
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432.9 433.1 433.3 433.5 433.7 433.9 434.1 434.3 434.5 434.7 434.9 FREQUENCY (MHz)
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Functional Diagram
CAGC UHF DOWNCOVERTER MIXER CONTROL LOGIC DESENSE AGC CONTROL
LNA MIXER
-f
f
IF AMP
DETECTOR
RSSI
RSSI
i fLO IMAGE REJECT FILTER CONTROL LOGIC PROGRAMMABLE FILTER OOK DEMODULATOR
SYNTHESIZER
SLICER
SLEEP OSCILLATOR
SLEEP TIMER
BITCHECK WAKE-UP SQUELCH
DO' DO CTH
AUTOPOLL
DO' DO REFERENCE OSCILLATOR
CONTROL LOGIC CONTROL LOGIC
SLICE LEVEL
REFERENCE AND CONTROL
Figure 1. Simplified Block Diagram.
Functional Description
The simplified block diagram, shown in Figure 1, illustrates the basic structure of the MICRF219 receiver. It is made up of four sub-blocks: * UHF Down-converter * OOK Demodulator * Reference and Control logic * Auto-poll circuitry Outside the device, the MICRF219 receiver requires just three components to operate: two capacitors (CTH, and CAGC) and the reference frequency device (usually a quartz crystal). An additional five components are used to improve performance; a power supply decoupling capacitor, two components for the matching network, and two components for the pre-selector band-pass filter.
Receiver Operation
UHF Downconverter The UHF down-converter has six components: LNA, mixers, synthesizer, image reject filter, band pass filter and IF amp. LNA The RF input signal is AC-coupled into the gate circuit of the grounded source LNA input stage. The LNA is a Cascoded NMOS amplifier. The amplified RF signal is then fed to the RF ports of two double balanced mixers. Mixers and Synthesizer The LO ports of the Mixers are driven by quadrature local oscillator outputs from the synthesizer block. The local oscillator signal from the synthesizer is placed on the low side of the desired RF signal to allow 6
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Micrel suppression of the image frequency at twice the IF frequency below the wanted signal. The local oscillator is set to 32 times the crystal reference frequency via a phase-locked loop synthesizer with a fully integrated loop filter. Image-Reject Filter and Band-Pass Filter The IF ports of the mixer produce quadrature-down converted IF signals. These IF signals are low-pass filtered to remove higher frequency products prior to the image reject filter where they are combined to reject the image frequencies. The IF signal then passes through a third order band pass filter. The IF center frequency is 1.2MHz. The IF BW is 330kHz @ 433.92MHz. This varies with RF operating frequency. The IF BW can be calculated via direct scaling:
MICRF219
SEL0 0 1 0 1
SEL1 0 0 1 1
Demod BW (@ 434MHz) 1625Hz 3250Hz 6500Hz 13000Hz - default
Table 1. Demodulation BW Selection
BWIF = BWIF@433.92 MHz x
Operating Freq (MHz) 433.92
These filters are fully integrated inside the MICRF219. After filtering, four active gain controlled amplifier stages enhance the IF signal to its proper level for demodulation. OOK Demodulator The demodulator section is comprised of detector, programmable low pass filter, slicer, and AGC comparator. Detector and Programmable Low-Pass Filter The demodulation starts with the detector removing the carrier from the IF signal. Post detection, the signal becomes base band information. The programmable low-pass filter further enhances the baseband information. There are four programmable low-pass filter BW settings: 1625Hz, 3250Hz, 6500Hz, 13000Hz for 433.92MHz operation. Low pass filter BW will vary with RF Operating Frequency. Filter BW values can be easily calculated by direct scaling. See equation below for filter BW calculation:
Slicer and Slicing Level The signal, prior to the slicer, is still AM. The data slicer converts the AM signal into ones and zeros based on the threshold voltage built up in the CTH capacitor. After the slicer, the signal is ASK or OOK digital data. The slicing threshold is default at 50%. The slicing threshold can be set via serial programming through register D5 and D6.
D5 1 0 1 0 D6 0 1 1 0 Slicing Level Slice Level 30% Slice Level 40% Slice Level 50% Slice Level 60% - default
AGC Comparator The AGC comparator monitors the signal amplitude from the output of the programmable low-pass filter. When the output signal is less than 750mV thresh-hold, 1.5A current is sourced into the external CAGC capacitor. When the output signal is greater than 750mV, a 15A current sink discharges the CAGC capacitor. The voltage developed on the CAGC capacitor acts to adjust the gain of the mixer and the IF amplifier to compensate for RF input signal level variation.
Operating Freq (MHz) BWOperating Freq = BW@433.92MHz* 433.92 It is very important to choose filter setting that fits best the intended data rate to minimize data distortion. Demod BW is set at 13000Hz @ 433.92MHz as default (assuming both SEL0 and SEL1 pins are floating). The low pass filter can be hardware set by external pins SEL0 and SEL1.
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Desense Desense is a function designed to reduce the sensitivity of the MICRF219 receiver to a maximum of 45dB for training the MICRF219 receiver. This is done in order to recognize an intended transmitter. Very often, a receiver needs to learn how to recognize a particular transmitter. It is important for the receiver not to learn the signal of a stray transmitter near by. The simplest solution is to turn down the receiver gain, so the receiver only recognizes the transmitter at close range. The de-sense function is accessible only through serial programming.
D0 D1 D2 MODE: Desense
Reference Control There are 2 components in Reference and Control subblock: 1) Reference Oscillator and 2) Control Logic through parallel Inputs: SEL0, SEL1, SHDN Reference Oscillator The reference oscillator in the MICRF219 (Figure 2. Reference Oscillator Circuit) uses a basic Pierce crystal oscillator configuration with MOS transconductor to provide negative resistance. Though the MICRF219 has build-in load capacitors for the crystal oscillator, the external load capacitors are still required for tuning it to the right frequency. R01 and R02 are external pins of the MICRF219 to connect the crystal to the reference oscillator. Reference oscillator crystal frequency can be calculated: FREF OSC = FRF/(32 + 1.1/12) For 433.92 MHz, FREF OSC = 13.52127 MHz. To operate the MICRF219 with minimum offset, crystal frequencies should be specified with 10pF loading capacitance.
0 1 1 1 1
X 0 1 0 1
X 0 0 1 1
No Desense - default 6dB Desense 16dB Desense 30dB Desense 42dB Desense
RO2 C R RO1 C V BIAS
Figure 2. Reference Oscillator Circuit
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SQUELCH Decode Data Edge Pulses CLK DOUT CLK Edge Detector CLK Window Counter D 8 Stage Shift Register >=7 Good R <=4 Good S Q
MICRF219
SQUELCH Disables DO
Window Decode
Decode Bad Bits Good Bit QA1 Bad Bit Returns to SLEEP
Decode Good Bit Count
CLK WATCHDOG Timer Auto Poll S Serial Control Register R
D7 D8 Select 0, 2, 4, 8 Good Bits Before Wakeup WAKEUP Timer (300s) D15 = 0 for Normal Operation D15 = 1 for Auto Polled Operation
D15
Figure 3. Autopoll, Bit-Check Block Diagram
Auto-Polling
The auto-poll block (Figure 3) contains a low power oscillator that drives the sleep timer when the rest of the device is powered down. It also contains circuits to check whether the received bits are good. Autopolling is controlled by bit D15 in the serial register, in conjunction with bits D12, D13, D14 to set the sleep timer period. Bits D7, D8, are used for control of the bit-check operation and bits D9, D10, D11 are used to adjust the sensitivity of the bit-check action. Auto-Polling without Bit-Checking For simple auto-polling without bit-checking, send a serial command with bit D15 set high and bits D12, D13, D14 set to the desired sleep time. The device will go to sleep for the programmed timer duration then wake up to receive data if it is present. The device will stay awake until serial bit D15 is set low, then set high again, to enable a further sleep period. The sleep duty cycle may be controlled by the timing of serial commands. Auto-Polling with Bit-Checking For auto-polling with bit-checking, the serial register bits D7and D8 need to be set for the number of bits to be checked as good, before the receiver outputs data at the DO pin. The bit-check window bits D9, D10, D11 must also be set to match the data period. The shortest default window time gives the least critical bit check action. For better discrimination, the window setting may be increased up towards the normal minimum time expected between data edges. Note that a window time set longer than this will result in all bits being tested as bad and the device will remain in sleep polling mode. Now, when the serial command sets bit D15 high, the device will go to sleep for the timer period and will then awake to receive and check bits. The device will output data again at DO as soon as the programmed numbers of good RTZ bits have been received. If a bad bit is seen, the device will return to sleep mode and poll again for good bits after the timeout period. Both high and low periods are checked for each RTZ bit. If data transitions are not received, the device will return to sleep after the bitcheck watchdog timeout period unless bit D18 has been sent. In this case the device will continue to check bits until sufficient good bits enable the device to wake up, or bad bits return the device to sleep.
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MICRF219 timeout period.
Squelch During normal operation, if four or less out of eight bit pulses are good, the DO output is squelched. If good bit count increases to seven or more in any eight sequential bits, squelch is disabled allowing data to output at DO pin.
D9 D10 Set D3 to Set D4 to 0 0 1 1 0 0 1 1 D10 Set D3 to Set D4 to 0 0 1 1 0 0 1 1 D11 MODE: Bit-Check Window Times (315 MHz) D3=1 D3=0 D3=1 D3=0 D4=1 D4=1 D4=0 D4=0 98us, 196us, 393us, 785us 92us, 183us, 367us, 733us 85us, 170us, 341us, 681us 79us, 157us, 314us, 629us 72us, 144us, 288us, 577us 66us, 131us, 262us, 525us 59us, 118us, 236us, 473us 53us, 105us, 210us, 420us MODE: Bit-Check Window Times (433.92MHz) D3=1 D3=0 D3=1 D3=0 D4=1 D4=1 D4=0 D4=0 71us, 143us, 285us, 570us 67us, 133us, 266us, 532us 62us, 124us, 247us, 494us 57us, 114us, 228us, 457us 52us, 105us, 209us, 419us 48us, 95us, 190us, 381us 43us, 86us, 172us, 343us 38us, 76us, 152us, 305us
Operation Received pulse edges trigger a programmable window timer clocked by the reference frequency. If the next pulse edge falls within this window the bit is flagged as bad. Detected good bits are counted and the device will wake up once sufficient pulses have been received. Two bad pulses or a lack of pulses will cause the device to go to sleep for a further sleep
Serial Interface Register Programming
Control Register Individual Truth Tables:
D0 0 1 1 1 1 D3 0 1 0 1 D5 1 0 1 0 D7 0 1 0 1 D1 X 0 1 0 1 D4 0 0 1 1 D6 0 1 1 0 D8 0 0 1 1 D2 X 0 0 1 1 MODE: Desense No Desense - default 6dB Desense 16dB Desense 30dB Desense 42dB Desense
MODE: Demod Bandwidth (at 433.92MHz) 1625Hz 3250Hz 6500Hz 13000Hz - default MODE Slice Level 30% Slice Level 40% Slice Level 50% Slice Level 60%
0 1 0 1 0 1 0 1 D9
0 0 0 0 1 1 1 1 D11
- default
MODE: Bit-Check Setting Bit-check 0 bits - default Bit-check 2 bits Bit-check 4 bits Bit-check 8 bits
0 1 0 1 0 1 0 1
0 0 0 0 1 1 1 1
Default State D9, D10, D11 is 111 D12 0 1 0 1 0 1 0 1 D15 0 1 D13 0 0 1 1 0 0 1 1 D14 0 0 0 0 1 1 1 1 MODE: Sleep Time 10ms 20ms 40ms Default 80ms 160ms 320ms 640ms 1280ms
MODE: Auto-Poll Awake - does not poll - default Auto-polls with Sleep periods
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D16 0 1 SQ Pin 0 0 1 1 MODE: Demod BW Select Normal Demod BW's - default Fast Demod BW's, (not available) D17 0 1 0 1 MODE: Squelch Enable Squelch Circuit Enabled Squelch Circuit Disabled Squelch Circuit Disabled (default) Squelch Circuit Enabled
MICRF219
D19 0 1 D19
MODE: RSSI RSSI offset 0mV - default RSSI offset +200mV MODE: Fast AGC Settling Disable
0 1
All improved fast attack AGC and CTH hold circuits are enabled - default Fast attack and CTH hold operation is disabled
The external pin SQ can invert the setting of squelch on/off defined by register bit D17. The external pin defaults high via an internal pull-up so the squelch is off with default D17 = 0 and on if D17 = 1. Such bit logic is reversed if SQ pin is tied to low (Ground).
D18 MODE: Bit-Check Watchdog Timeout Sleep polling watchdog active - default Watchdog time for D3, D4, BW setting 0 0 20ms 0 1 5ms 1 0 10ms 1 1 5ms Sleep polling watchdog disabled - unlimited poll period D3 D4
0
1
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Application Information
Figure 4. QR219BPF Application Example, 433.92 MHz
Antenna and RF Port Connections Figure 4 shows the schematic of the QR219BPF configured for 433.29 MHz operation. Figures 19-23 are PCB pictures. The QR219BPF is a good starting point for the prototyping of most applications. Current design offers two antenna options: A wire antenna or 50 SMA antenna. The SMA connection also allows an RF signal to be injected for test or verification. To use an antenna such as a 50 whip, remove the SMA and solder the whip antenna in the hole on the PCB instead. A wire of 22AWG with 167mm (6.-inch) can be used as a substitution if low cost antenna is needed. Front-End Band Pass Filter Components L1 and C8 form the band-pass filter at front of the receiver. Its purpose is to attenuate undesired outside band noise that degrades the receiver performance. It is calculated by the parallel resonance equation: f = 1/(2xPIx(SQRT L1xC8)). Table 2 shows the component values for most often used frequencies.
Freq (MHz) 315.0 390.0 418.0 433.92
C8 (pF) 6.8 6.8 6.0 5.6
L1(nH) 39 24 24 24
Table 2. Front Band-Pass Filter values for various frequencies
This band-pass filter can be removed if the outside band noise does not cause a problem. The MICRF219 has built-in image reject mixers which improve the selectivity significantly and reject outside band noise.
Low-Noise Amplifier Input Matching Capacitor C3 and inductor L2 form the "L" shape input matching network. The capacitor provides additional attenuation for low-frequency outside band noise. The inductor provides additional ESD protection for the antenna pin. Two methods can be used to find these values that best matched near 50. One method is done by calculating the values using the equations below and the other is using a Smith chart utility. The latter is made easier via a software plot where components are added on. In this way, the user 12
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can see the impedance moving direction for best values of C8 and L1 toward to central matching point, like WinSmith by Noble Publishing. To calculate the matching values, one needs to know the input impedance of the device. Table 3 shows the input impedance of the MICRF219 and suggested matching values for the most often used frequencies. These suggested values may be different if the layout is not exactly the same as the one made here.
Freq (MHz) 315 390 418 433.92 C3 (pF) 1.8 1.5 1.5 1.5 L2(nH) 68 47 43 39 Z device () 33 - j235 23 - j199 21 - j186 19 - j174
Table 3. Matching values for the most used frequencies
For the frequency of 433.92MHz, the input impedance is Z = 18.6 - j174.2, then the matching components are calculated by, Equivalent parallel = B = 1/Z = 0.606 + j5.68 msiemens Rp = 1 / Re (B); Xp = 1 / Im (B) Rp = 1.65k; Xp = 176.2 Q = SQRT (Rp/50 + 1) Q = 5.831 Xm = Rp / Q Xm = 282.98 Resonance Method For L-shape Matching Network Lc = Xp / (2xPixf); Lp = Xm / (2xPixf) L2 = (LcxLp) / (Lc + Lp); C3 = 1 / (2xPixfxXm) L2 = 39.8nH C3 = 1.3pF Doing the same calculation example with the Smith Chart, would appear as follows, First, one plots the input impedance of the device, (Z = 18.6 - j174.2) @ 433.92MHz.(Figure 5).
Figure 5. Device's input impedance, Z = 19 - j174
Second, one plots the shunt inductor (39nH) and the series capacitor (1.5pF) for the desired input impedance (Figure 6). One can then see the matching leading to the center of the Smith Chart or close to 50.
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MICRF219 oscillator. Good care must be taken when laying out the printed circuit board. Avoid long traces and place the ground plane on the top layer close to the REFOSC pins RO1 and RO2. When care is not taken in the layout, and the crystals used are not verified, the oscillator may take longer time to start. Time-togood-data in the DO pin will be longer as well. In some cases, if the stray capacitance is too high (> 20pF). In this case, either the receiving central frequency will offset too much or the oscillator may not start. The crystal frequency is calculated by REFOSC = RF Carrier/(32+(1.1/12)). The local oscillator is low side injection (32 x 13.52127MHz = 432.68MHz), that is, its frequency is below the RF carrier frequency and the image frequency is below the LO frequency. See Figure 7. The product of the incoming RF signal and local oscillator signal will yield the IF frequency, which will be demodulated by the detector of the device.
Figure 6. Plotting of shunt inductor and series capacitor.
Crystal Selection Crystal Y1 or Y1A (SMT or leaded respectively) is the reference clock for all the device internal circuits. Crystal characteristics of 10pF load capacitance, 30ppm, ESR < 50, -40C to +105C temperature range are desired. Table 5 shows Micrel's approved crystal suppliers such as (www.hib.com.br or http://www.abracon.com/ ) and the frequencies. The oscillator of the MICRF219 is a Pierce-type
REFOSC (MHz) 9.81563 12.15269 13.02519 13.52127 Carrier (MHz) 315.0 390.0 418.0 433.92
Figure 7. Low Side Injection Local Oscillator.
HIB Part Number SA-9.815630-F-10-H-30-30-X SA-12.152690-F-10-H-30-30-X SA-13.025190-F-10-H-30-30-X SA-13.521270-F-10-H-30-30-X
Abracon Part Number ABLS-9.81563MHz-10J4Y ABLS-12.15269MHz-10J4Y ABLS-13.025190MHz-10J4Y ABLS-13.521270MHz-10J4Y
Table 4. Crystal Frequencies and Vendor Part Numbers.
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SEL0 JP1 SEL1 JP2 Demod. BW (hertz) 1170 2350 4700 9400 Shortest Pulse (sec) 445 223 111 56
MICRF219
Maximum baud rate for 50% Duty Cycle (Hz) 1123 2246 4493 8987
Demodulator Bandwidth Selection and Data Stream Optimization JP1 and JP2 are the bandwidth selection for the demodulator bandwidth. To set it correctly, it is necessary to know the shortest pulse width of the encoded data sent in the transmitter. Similar to the example of the data profile in the Figure 7 below, PW2 is shorter than PW1, so PW2 should be used for the demodulator bandwidth calculation which is found by 0.65/shortest pulse width. After this value is found, the setting should be done according to Error! Reference source not found.. For example, if the pulse period is 100sec, 50% duty cycle, the pulse width will be 50sec (PW = (100sec x 50%) / 100). Therefore, a bandwidth of 13kHz would be necessary (0.65 / 50sec). However, if this data stream had a pulse period with a 20% duty cycle, then the bandwidth required would be 32.5kHz (0.65 / 20sec). This would exceed the maximum bandwidth of the demodulator circuit. If one tries to exceed the maximum bandwidth, the pulse would appear stretched or wider.
SEL0 JP1 SEL1 JP2 Demod. BW (hertz) Shortest Pulse (sec) Maximum baud rate for 50% Duty Cycle (Hz)
Short Open Short Open
Short Short Open Open
Table 7. JP1 and JP2 setting, 315 MHz.
AGC Capacitor and Data Slicer Threshold Capacitor Seletion Capacitors C6 and C4 are CTH and CAGC capacitors respectively providing a time base reference for the data pattern received. These capacitors are selected according to data profile, pulse duty cycle, dead time between two received data packets, and if the data pattern does has or not have a preamble. See Figure 8 for example of a data profile.
Short Open Short Open
Short Short Open Open
1625 3250 6500 13000
400 200 100 50
1250 2500 5000 10000 Figure 8. Example of a Data Profile.
Table 5. JP1 and JP2 setting, 433.92 MHz.
Other frequencies will have different demodulator bandwidth limits, which is derived from the reference oscillator frequency. Error! Reference source not found. and Table 7 below shows the limits for the other two most used frequencies.
SEL0 JP1 SEL1 JP2 Demod. BW (hertz) Shortest Pulse (sec) Maximum baud rate for 50% Duty Cycle (Hz)
For best results, they should always be optimized for the data pattern used. As the baud rate increases, the capacitor values decrease. Table 8 shows suggested values for Manchester Encoded data, 50% duty cycle.
SEL0 JP1 Short Open Short Open SEL1 JP2 Short Short Open Open Demod. BW (hertz) 1625 3250 6500 13000 Cth Cagc
100nF 47nF 22nF 10nF
4.7F 2.2F 1F 0.47F
Short Open Short Open
Short Short Open Open
1565 3130 6261 12523
416 208 104 52
1204 2408 4816 9633
Table 8. Suggested CTH and CAGC Values.
Table 6. JP1 and JP2 setting, 418.0 MHz.
JP3 and JP4 are jumpers selectable to high or low and used to configure the digital squelch function. When it is tied to high, there is no squelch applied to the digital circuits and the DO (data out) pin has a hash signal. When the pin is low, the DO pin activity is considerably reduced. It will have more or less than
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MICRF219 voltage in this AGC pin to purposely decrease the device sensitivity. Special care is needed when doing this operation, as an external control of the AGC voltage may vary from lot to lot and may not work the same in several devices. Three other pins are worthy of comment. They are the DO, RSSI, and shutdown pins. The DO pin has a driving capability of 0.4mA. This is good enough for most of the logic family ICs on the market today. The RSSI pin provides a transfer function of the RF signal intensity versus voltage. It is very useful to determine the signal-to-noise ratio of the RF link, crude range estimate from the transmitter source and AM demodulation, which requires a low CAGC capacitor value. The shutdown pin (SHDN) is useful to save energy. Making its level close to VDD (SHDN = 1), the device is not in operation. Its DC current consumption is less than 1A (do not forget to remove R3). When toggling from high to low, there will be a time required for the device to come to steady-state mode, and a time for data to show up in the DO pin. This time will be dependent upon many things such as temperature, the crystal used, and if there is an external oscillator with faster startup time. See Figure 11 and 12 for time-to-good-data on both 433.92MHz and 315MHz versions.
shown in the figure below depending upon the outside band noise. The penalty for using squelch is a delay in getting a good signal in the DO pin. This mean that it takes longer for the data to show up. The delay is dependent upon many factors such as RF signal intensity, data profile, data rate, CTH and CAGC capacitor values, and outside band noise. See Figure 9 and Figure 10 below. Please note that Squelch action is based on the Bitcheck operation and may be optimized using the Bitcheck Window serial register setting.
Figure 9. Data Out Pin with No Squelch (SQ = 1).
Figure 10. Data Out Pin with Squelch (SQ = 0).
Figure 11. Time-to-Good-Data After Shut Down Cycle, 433.92MHz, Room Temperature.
Other components used are C5, which is a decoupling capacitor for the Vdd line; R3 for the shutdown pin (SHDN = 0, device is operation), which can be removed if that pin is connected to a microcontroller or an external switch; and R1 and R2 which form a voltage divider for the AGC pin. One can force a
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Figure 12. Time-to-Good-Data After Shut Down Cycle, 315MHz at Room Temperature.
Serial Register Programming
Programming the device is accomplished by the use of pins DO and SCLK. Normally, D0 (Pin 10) is outputting data and needs to switch to an input pin made by the start sequence, as shown at Figure 13. High at the SCLK pin tri-states the DO pin, enabling the external drive into the DO pin with an initial low level. The start sequence is completed by taking SCLK low, then high while DO is low, followed by taking DO high, then low while SCLK is high. The serial interface is initialized and ready to receive the programming data.
T6 SCLK T7 BIT TIME 0 BIT TIME 1 BIT TIME 2
are programmed as needed. It is recommended that all parallel input pins (SEL0, SEL1, and SQ) be kept high when using the serial interface. After the programming bits are finished, a stop sequence (as shown in Figure 14) is required to end the mode and reestablish the DO pin as an output again. To do so, the SCLK pin is kept high while the DO pin changes from low to high, then low again, followed by the SCLK pin made low. Timing of the programming bits are not critical, but should be kept as shown below: T1 < 0.1 us, Time from SCLK to convert DO to input pin T6 > 0.1 us, SCLK high time T7 > 0.1 us, SCLK low time T2, T3, T4, T5, T8, T9, T10 > 0.1 us
BIT TIME 18 BIT TIME 19
SCLK
T2 T3 T4 T5 T8 T9
T1
T10 "1"
"19" DO AS OUTPUT DO INPUT BITS: D19 "0" D18 "0" D17 "1"
"0" DO
"1"
DO DO PIN AS OUTPUT
D1
Figure 14. Serial Interface Stop Sequence.
Figure 13. Serial Interface Start Sequence.
Bits are serially programmed starting with the most significant bit (MSB = D19) if all bits are being programmed until the least significant bit (LSB =D0) For instance, if only the desense bits D0, D1, and D2 are being programmed, then these are the only bits that need to be programmed with the start sequence D2, D1, D0, plus the stop sequence. Or, if only the squelch bit D17 is needed, then the sequence must be from start sequence, D17 through D0 plus the stop sequence, making sure the other bits (besides D17)
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MICRF219
Serial Interface Register Loading Examples See Figures 15 - 17. (Channel 1 is the DO pin, and channel 2 is the SCLK pin).
Figure 17. D19 = D18 = 1, D17 = D0 = 0 Auto-Poll Programming Example Auto-Poll example, see Figure 18 D0 = D1 = D2 = 0, no desense D3 = D4 = 0, demodulator bandwidth = 1712 hertz, 1 kHz baud rate, pulse = 500 usec. Required demodulator bandwidth is 0.65/500usec = 1300 hertz D5 = D6 = 1, Slice level = 50% D7 = 0, D8 = 1, bit check = 4 bits. This is the time the device is ON checking for four consecutive valid windows. D9 = D10 = 1, D11 = 0, data rate is 1 kHz, (500 usec pulses), window set to 433 usec (< 500 usec) D12 = D13 = 0, D14 = 1, sleep timer set to 160 msec, that is, 4 bit is ON and 160 msec is OFF. D15 = 1, device is placed in autopoll D16 = 0, not used. Always set to 0. D17 = 0, squelch is OFF D18 = 1, watchdog timer is OFF D19 = 0, no RSSI offset
Figure 15. All bits D19 through D0 = 0
Figure 16. All bits D19 through D0 = 1
From MSB to LSB, see Table 9:
D19 D18 D17 D16 D15 D14 D13 D12
0
D11 0 D4 0
1
D10 1 D3 0
0
D9 1 D2 0
0
D8 1 D1 0
1
D7 0 D0 0
1
D6 1
0
D5 1
0
Table 9. Auto-Poll example bit sequence.
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MICRF219
Figure 18. Autopoll example
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MICRF219 inductance. Ground plane should be solid and with no sudden interruptions. Avoid using ground plane on top layer next to the matching elements. It normally adds additional stray capacitance which changes the matching. Do not use Phenolic materials as they are conductive above 200MHz. Typically, FR4 or better materials are recommended. The RF path should be as straight as possible to avoid loops and unnecessary turns. Separate ground and VDD lines from other digital or switching power circuits (such microcontroller...etc). Known sources of noise should be laid out as far as possible from the RF circuits. Avoid unnecessary wide traces which would add more distribution capacitance (between top trace to bottom GND plane) and alter the RF parameters.
PCB Considerations and Layout
Figure 19 to 23 below show the QR219BPF PCB layout. The Gerber files provided are downloadable from Micrel Website and contain the remaining layers needed to fabricate this board. When copying or making one's own boards, make the traces as short as possible. Long traces alter the matching network and the values suggested are no longer valid. Suggested matching values may vary due to PCB variations. A PCB trace 100 mills (2.5mm) long has about 1.1nH inductance. Optimization should always be done with exhaustive range tests. Make sure the individual ground connection has a dedicated via rather then sharing a few of ground points by a single via. Sharing ground via will increase the ground path
Figure 19. QR219BPF Top Layer
Figure 20. QR219BPF Bottom Layer
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MICRF219
Figure 21. QR219BPF Top Silkscreen Layer
Figure 22. QR219BPF Bottom Silkscreen Layer
Figure 23: QR219BPF Dimensions (in inches).
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MICRF219
QR219BPF Bill of Materials, 433.92 MHz
Item 1 2 3 4 5 6 7 Reference ANT1 C3 C4 C6,C5 C8 C10,C9 JP1,JP2,R5,R6,R7 Part 22AWG rigid wire 1.5pF 50V 4.7uF 6.3V 0.1uF 16V 5.6pF 50V 10pF 50V 0ohm
Description 167mm (6.6") 22AWG wire 0603 chip capacitor 0805 chip capacitor 0603 chip capacitor 0603 chip capacitor 0603 chip capacitor 0603 chip resistor 0603 chip resistor, not placed 7 pin connector Edge mount SMA connector 5%, 0603 SMT inductor 5%, 0603 SMT inductor 0603 chip resistor MICRF219 chip Crystal
Qty 1 1 1 2 1 2 5
8 9 10 11 12 13 14 15
R1,R2,JP3,JP4 J1 J2 L1 L2 R3 U1 Y1
(np) CON7 (np) 24nH 5% 39nH 5% 100kohm MICRF219AYQS 13.52127MHz
4 1 1 1 1 2 1 1
Table 10. QR219BPF Bill of Materials, 433.92 MHz.
QR219BPF Bill of Materials, 315 MHz
Item 1 2 3 4 5 6 7 Reference ANT1 C3 C4 C6,C5 C8 C10,C9 JP1,JP2,R5,R6,R7 Part 22AWG rigid wire 1.8pF 50V 4.7uF 6.3V 0.1uF 16V 6.8pF 50V 10pF 50V 0ohm
Description 230mm (9.0") 22AWG wire 0603 chip capacitor 0805 chip capacitor 0603 chip capacitor 0603 chip capacitor 0603 chip capacitor 0603 chip resistor 0603 chip resistor, not placed 7 pin connector Edge mount SMA connector 5%, 0603 SMT inductor 5%, 0603 SMT inductor 0603 chip resistor MICRF219 chip Crystal
Qty 1 1 1 2 1 2 5
8 9 10 11 12 13 14 15
R1,R2,JP3,JP4 J1 J2 L1 L2 R3 U1 Y1
(np) CON7 (np) 39nH 5% 68nH 5% 100kohm MICRF219AYQS 9.81563MHz
4 1 1 1 1 2 1 1
Table 11. QR219BPF Bill of Materials, 315 MHz.
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MICRF219
Package Information
QSOP16 Package Type (AQS16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2009 Micrel, Incorporated.
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MICRF219
Revision History
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